Exemplary embodiments of the present invention relate to a semiconductor chip and a semiconductor wafer, and more particularly, to a guard ring structure which physically separates chips on a semiconductor wafer from scribe line regions.
A semiconductor wafer manufactured by a typical fabrication process includes a plurality of semiconductor chips. Since processes performed on the semiconductor wafer are to have high accuracy, the semiconductor wafer undergoes several tests during the processes. For example, a PCM (Process Control Monitor) test may be performed to monitor characteristics of devices and circuits inside semiconductor chips, or a probe test may be performed to monitor operational characteristics of semiconductor chips. In order to perform those tests, test patterns or built-in self test (GIST) circuits are formed in scribe line regions or scribe lane regions, which are defined between semiconductor chips. In a package process after the semiconductor fabrication process, the semiconductor wafer is sawed into the semiconductor chips. At this time, the scribe line region is a sawing reference for separating the semiconductor wafer into individual chips. When the sawing process is performed on the semiconductor wafer during the package process, chip boundary regions are formed on four edges of the respective chips in order to prevent stress and moisture from being applied and penetrating into the semiconductor chips.
A related semiconductor wafer structure is illustrated in FIGS. 1A and 1B. A semiconductor wafer 10 includes a plurality of semiconductor chips (four chips in the drawings). Each of the semiconductor chips includes a device formation region and a chip boundary region. For example, a semiconductor chip 10A includes a device formation region 20A and a chip boundary region 30A surrounding four edges of the device formation region 20A. The remaining semiconductor chips 10B, 10C and 10D include device formation regions 20B, 20C and 20D and chip boundary regions 30B, 30C and 30D, respectively. Scribe line regions 40 are formed between the semiconductor chips 10A, 10B, 10C and 10D.
In the scribe line regions 40 as well as the chip boundary regions 30A, 30B, 30C and 30D, a structure for preventing external stress and moisture from being applied and penetrated into the device formation regions 20A, 20B, 20C and 20D is formed. Meanwhile, as described above, test patterns or test circuits for monitoring characteristics of the semiconductor chips 10A, 10B, 10C and 10D are implemented in the scribe line regions 40. Therefore, in order to perform the test operation through the test patterns or the test circuits, a guard ring structure for transferring signals between the semiconductor chips 10A, 10B, 10C and 10D and the scribe line regions 40 is useful.